The CPU:
General Purpose Registers:
CPU provides 32 GPRegisters each 32 bits long.
ro,r1,……,r31
they are used in procdeures calling, stack frame, returning values from procedure.
Control Registers:
they hold values that control the execution of the processor. All are 32 bits long.
ia- the instruction address register contains the address of next instruction
psw- program status word (2bit)bit 0 is 1 user mode, else kernel mode
bit 1 is 1 if interrupt is enabled and 0 is interrupt is masked.
iia- interrupt instruction address register stores the value of ia before an interrupt.
When an interrupt occurs, the value of ia is saved in iia, and the ia is loaded with the address of the interrupt handler.
base- memory base register is added to all the addresses when the system is in user mode.
bound- the memory bound register is the address limit.
In user mode all address must be less than the bound register, otherwise a program error interrupt will occur.
ipsw- interrupt program status word stores the value of psw register before an interrupt.
ip- interrupt parameter register contains data about the last interrupt.
iva-interrupt vector address register is the location in memory where the interrupt vector table is located.
Instruction Set:
load, store, loadAll, storeAll, move, syscall, rti(return from interrupt)
Questions:
Q1> how do we know interrupt is masked or active?
Q2> how do we know progam is running in user mode or system mode?
(hint check psw for both questions)
Q3>why do we have base and bound registers?
(hint: mapping logical address to physical address)
Q4) how does interrupt handle at lowlevel?
Answer: psw is saved in the ipsw register by the cpu. Reset psw it means
processor is in system mode with interrupt masked or disabled.
Stores the interrupt argument in the ip register.
save ia register to iia register, get the address of interrupt handler by checking iva register& load the address into the ia register.
I/O devices:
Memory Mapped IO: Communication between io devices and processor is done thru physical memory locations in the io address space.
Each device will have some locations in the memory.
Processor will respond when those locations are placed on the bus.
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